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In high-speed designs, timing requirements for the high-speed signals are met by matching the routed length of the signal path. For a two-pin signal path it’s very easy but for some typical design solutions though where there may be a series termination component in the signal path, or the signals are routed with a Balanced T or Fly-by topology creates the signal path with multiple pins and multiple nets right.

So what if more than two pins \nets are there in the signal path? How we can match those signals? How we can achieve the timing budget? The Solution is "X signals" All these can be managed by the Altium feature called "X signals".

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